Verification And Validation Process
- The process of comparing two levels of a system specification for proper correspondence or of proving that some property of a specification is correctly implemented by the system (e. g. , security policy model with top- level specification, top-level specification with source code with object). NOTE: Verification may be formal or informal, or automated or not automated. Formal verification is the process of using formal proofs (complete mathematical argument) to demonstrate the consistency between formal specification of a system and formal security policy model (design verification) or between formal specification and its high-level program implementation (implementation verification). Formal implies using a formal mathematical language.